Conventionally, the structure shown in FIG. 19 is known as an example of an A/D (analog/digital) conversion circuit (see, for example, Non-patent document 1). FIG. 19 shows the structure of a conventionally known A/D conversion circuit.
In the example shown in FIG. 19, an A/D conversion circuit 190 includes a pulse transit circuit 191, a counter 192, an encoder 193, a first latch circuit 194, a second latch circuit 195, a third latch circuit 196, and a computing device 197. In the pulse transit circuit 191, a single NAND (Negative AND) circuit 1911, which serves as a startup inverter circuit, and a plurality of inverter (INV) circuits 1912, which serve as inverter circuits, are connected in a ring shape. The NAND circuit 1911 operates by receiving a pulse signal StartP via one input terminal. The counter 192 and the encoder 193 measure output signals from the pulse transit circuit 191. The first latch circuit 194 holds output signals from the counter 192. The second latch circuit 195 holds output signals from the encoder 193. The third latch circuit 196 adds together output signals from the first latch circuit 194 and the second latch circuit 195, and holds the result. The computing device 197 computes a difference between a previous signal and a current signal using the third latch circuit 196, and outputs the result to an external latter-stage circuit.
Moreover, in the example shown in FIG. 19, a power supply line 1913 that supplies power to the NAND circuit 1911 and the inverter circuits 1912 of the pulse transit circuit 191 is connected to an input terminal 198. An analog input signal Vin which is to be subjected to A/D conversion is input into the input terminal 198. The encoder 193 and the first and second latch circuits 194 and 195 receive the input of a clock (CLK) signal CKs.
Next, operations of the A/D conversion circuit 190 will be described. As is shown in FIG. 19, in the pulse transit circuit 191, the pulse signal StartP transits around a circuit orbit formed by the single NAND circuit 1911 and the plurality of inverter circuits 1912 which are formed in a ring shape.
The pulse signal StartP changes in accordance with the size (i.e. the voltage) of the analog input signal Vin and the period of the clock (CLK) signal CKs. The counter 192 counts the number of times the pulse signal StartP transits around the circuit orbit within the pulse transit circuit 191, and outputs the result of this count as binary digital data. The encoder 193 detects the position of the pulse signal StartP in the circuit within the pulse transit circuit 191, and outputs this result as binary digital data.
The first latch circuit 194 holds digital data output by the counter 192. The second latch circuit 195 holds digital data output by the encoder 193. The third latch circuit 196 acquires the digital data held by the first latch circuit 194 as high-order bits, and acquires the digital data latched by the second latch circuit 195 as low-order bits, and adds together these groups of digital data. By doing this, the third latch circuit 196 creates and holds binary digital data that corresponds to the size of the analog input signal Vin for each period of the clock signal CKs.
The computing device 197 computes the difference between the digital data held by the third latch circuit 196 and the previous digital data held by the latch circuit 196, and outputs the computed digital data DT to the external latter-stage circuit.
FIG. 20 is a graph showing a relationship between the size of the analog input signal Vin in the A/D conversion circuit 190, and the propagation delay time of the pulse signal StartP transiting within the circuit. In the A/D conversion circuit 190, if the size of the analog input signal Vin is small, the propagation delay time of the pulse signal StartP increases, while if the size of the analog input signal Vin is large, the propagation delay time of the pulse signal StartP decreases. Accordingly, digital data that corresponds to the propagation delay time of this pulse signal StartP is output from the A/D conversion circuit 190.
FIG. 21 is a drawing showing a relationship between the sampling period in the A/D conversion circuit 190 and the timings at which digital data is output. The A/D conversion circuit 190 periodically outputs the digital data DT for each period of the clock signal CKs which is a sampling period. In the example shown in the drawing, digital data 2121 is output in the sampling period 2111, digital data 2122 is output in the sampling period 2112, and digital data 2123 is output in the sampling period 2113.
As is described above, the A/D conversion circuit 190 periodically outputs digital data DT that corresponds to the size of the analog input signal Vin for each period of the clock signal CKs.    [Non-patent document 1] “An All-Digital Analog-to-Digital Converter With 12-μ V/LSB Using Moving-Average Filtering”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2002